1. Field of the Invention
The present invention relates to an apparatus and processes for electrically localizing site-specific defects in sub-micron MOSFET devices.
2. Description of Related Art
Transmission electron microscopes (TEMs) are commonly used in the process of fabricating integrated circuits. TEMs are used to microscopically examine portions of a semiconductor die to determine the results of new or conventional processes. The examination may be to confirm the results of an experimental process, to determine the nature of a particular failure or defect in a semiconductor device, or even to find impurities within the semiconductor device. Of course, because of the nature of integrated circuits, the examination must often be performed on samples cut from the die in question.
Examination of a wafer for impurities is crucial in the semiconductor fabrication process as certain impurities, in certain concentrations and within specific materials, typically cause semiconductor device failure. In so doing, the wafer is removed from the production line, or the fully processed die in a completely finished semiconductor package, is brought to an analytical tool to inspect for any impurities, such as, inspection via a TEM tool.
Conventional imaging techniques include the use of electron holography in TEM tools. This frequently involves using focused ion beam microscopy (FIB). Focused ion beams (FIB) are commonly relied on for the spatially localized preparation, repair and editing of integrated circuits. With the use of FIB, ion beams are typically generated by an FIB tool, which utilizes a liquid metal ion source, typically gallium (Ga+), from which highly energetic beams (E>30 keV) are formed and then focused onto the sample surface by electrostatic lenses. However, exposure to these highly energetic ion beams often causes IC damage, gallium contamination, and physical sputtering of the sample surface.
As the demand for higher performance integrated circuits dictates smaller critical dimension feature sizes with shallower implant junction depths and ever thinner MOSFET gate films, the use of FIB processing will also increase. Currently, a number of techniques exist in the art for electron holography and sample preparation using FIB microscopy for transmission electron microscopy (TEM). However, the art is deficient in TEM holography techniques to verify site-specific defects in sub-micron devices, i.e., 130 nm and smaller, due to limitations in electrical characterization isolation, sample surface preparation methods and requirements for uniformity thickness.
Current techniques are not reliable or sufficient for electrically isolating or imaging site-specific defects in these sub-micron MOSFET junctions. In fabricating smaller samples, it would be advantageous to have a processing method that enables the electrical isolation of site-specific defects in MOSFET devices for sub 130 nm sized devices with gate oxide/gate nitridized films less than 2 nm in thickness or with ALD (atomic layer deposited) high dielectric constant gate films. Therefore, a need continues to exist in the art for improved methods of electrically cally localizing site-specific defects in sub-micron MOSFET devices.